220 39336 <pj78nm$loi$1@blaine.gmane.org> article
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From: David Brown <david@westcontrol.com>
Newsgroups: gmane.comp.lang.c++.isocpp.proposals
Subject: Re: Alternative proposal for mapping P0709
 Deterministic Exceptions into C
Date: Tue, 24 Jul 2018 15:16:42 +0200
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On 24/07/18 12:38, Niall Douglas wrote:
> The pipeline bubbles you refer to only occur when testing more than
> one CPU flag at a time. One of the main reasons for choosing the
> carry bit as return discriminant is because there are instructions
> for testing just the carry bit alone on all such architectures. Thus
> such partial flags stalls will never occur in this specific use
> case.
> 

I am reluctant to be so confident about the effects here - I really
don't think you can generalise and say these stalls will never occur.  I
think it will depend a lot on the cpu ISA, the details of its
implementation (scheduling, out-of-order execution, register renaming,
pipelining, speculative execution, etc.), and the type of code you are
dealing with.  On many cpus, there are quite a lot of instructions that
use or affect the carry flag (or any other flags) - these pose a
challenge for scheduling.  They also pose a challenge for the compiler,
if it would want to use such instructions between the call to "foo" and
the check for "foo.error".

It may be fair to say that using the carry flag here would not cause
much in the way of stalling or delays - but I would not say "never"
without a lot more thorough analysis with a range of different processors.

On a related point, many compilers do not track the state of flags
across instruction pattern boundaries - /any/ use of a carry flag like
this would involve significant engineering effort.


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