220 39332 <pj6qkr$elo$1@blaine.gmane.org> article
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From: David Brown <david@westcontrol.com>
Newsgroups: gmane.comp.lang.c++.isocpp.proposals
Subject: Re: Alternative proposal for mapping P0709
 Deterministic Exceptions into C
Date: Tue, 24 Jul 2018 11:16:14 +0200
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On 23/07/18 10:11, Niall Douglas wrote:
>     Overall, do we really need this 'expected' kind of type to be quite
>     so constrained and magic, to require an even address etc. etc.
>     In other words, if the type was actually something that was
>     specified as a 'normal' C/C++ struct without any of those gymnastics
>     and data packing or require some carry register etc., would the code
>     be that dramatically worse that we should require such magic or
>     constraints than a regular type without all the magic and alignment
>     requirements?
> 
> Not speaking for the above proposal, but in general, it is currently
> believed that using something like the CPU carry bit ought to be zero
> overhead on most CPUs, whereas a discriminant stored in the layout would
> not be zero overhead on more CPUs.

For some cpus, there are cheap flags like this.  (Some cpus even have
"return with carry flag set" and "return with carry flag clear"
instructions that are tailor-made for such usage.)  On many bigger cpus,
however, working with flags can cause stalls in the processor pipelines
- the flag becomes a bottleneck dependency.  It is precisely for that
reason that RISC-V and some other newer designs have no flags.

> 
> The situation of RISC-V, which has no status register, is a particular
> unknown. Our current best guess is that either we keep the discriminant
> in the structure, or we fiddle with the return address e.g. offset it by
> four. There are no good options on that architecture.
> 
> Niall 
> 


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