220 39310 article Path: news.gmane.org!.POSTED!not-for-mail From: inkwizytoryankes@gmail.com Newsgroups: gmane.comp.lang.c++.isocpp.proposals Subject: Re: Alternative proposal for mapping P0709 Deterministic Exceptions into C Date: Mon, 23 Jul 2018 10:30:12 -0700 (PDT) Lines: 99 Approved: news@gmane.org Message-ID: References: <6a65c934-5d2a-4e75-b88d-9eaaee338bd3@isocpp.org> <87240a3d-623f-4f7f-8e7c-fa8c9482fa72@isocpp.org> <5a449c86-b0f4-4b07-b5d6-21b7adbfd63b@isocpp.org> Reply-To: std-proposals@isocpp.org NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_8519_1714243726.1532367012993" X-Trace: blaine.gmane.org 1532366890 20520 195.159.176.226 (23 Jul 2018 17:28:10 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Mon, 23 Jul 2018 17:28:10 +0000 (UTC) To: ISO C++ Standard - Future Proposals Original-X-From: std-proposals+bncBDDLTAGNTIBBBJNB3DNAKGQEOM3DPKY@isocpp.org Mon Jul 23 19:28:06 2018 Return-path: Envelope-to: gclcip-std-proposals@m.gmane.org Original-Received: from mail-yw0-f200.google.com ([209.85.161.200]) by blaine.gmane.org with esmtp (Exim 4.84_2) (envelope-from ) id 1fhect-0005CW-Pi for gclcip-std-proposals@m.gmane.org; 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Mon, 23 Jul 2018 10:30:14 -0700 (PDT) X-BeenThere: std-proposals@isocpp.org Original-Received: by 2002:a81:a703:: with SMTP id e3-v6ls1104255ywh.37.gmail; Mon, 23 Jul 2018 10:30:13 -0700 (PDT) X-Received: by 2002:a81:78c6:: with SMTP id t189-v6mr265273ywc.7.1532367013679; Mon, 23 Jul 2018 10:30:13 -0700 (PDT) In-Reply-To: <5a449c86-b0f4-4b07-b5d6-21b7adbfd63b@isocpp.org> X-Original-Sender: inkwizytoryankes@gmail.com Precedence: list Mailing-list: list std-proposals@isocpp.org; contact std-proposals+owners@isocpp.org List-ID: X-Spam-Checked-In-Group: std-proposals@isocpp.org X-Google-Group-Id: 399137483710 List-Post: , List-Help: , List-Archive: List-Subscribe: , List-Unsubscribe: , Xref: news.gmane.org gmane.comp.lang.c++.isocpp.proposals:39310 Archived-At: ------=_Part_8519_1714243726.1532367012993 Content-Type: multipart/alternative; boundary="----=_Part_8520_1785100287.1532367012993" ------=_Part_8520_1785100287.1532367012993 Content-Type: text/plain; charset="UTF-8" On Monday, July 23, 2018 at 10:11:45 AM UTC+2, Niall Douglas wrote: > > Overall, do we really need this 'expected' kind of type to be quite so >> constrained and magic, to require an even address etc. etc. >> In other words, if the type was actually something that was specified as >> a 'normal' C/C++ struct without any of those gymnastics and data packing >> or require some carry register etc., would the code be that dramatically >> worse that we should require such magic or constraints than a regular type >> without all the magic and alignment requirements? >> >> Not speaking for the above proposal, but in general, it is currently > believed that using something like the CPU carry bit ought to be zero > overhead on most CPUs, whereas a discriminant stored in the layout would > not be zero overhead on more CPUs. > > The situation of RISC-V, which has no status register, is a particular > unknown. Our current best guess is that either we keep the discriminant in > the structure, or we fiddle with the return address e.g. offset it by four. > There are no good options on that architecture. > > Niall > On RISC-V then cost will be same to `bool foo(void* ret)`. This will be still "zero overhead", simply for other architectures it will be "negative overhead" compared to equivalent manual checks in code. Another way could be use RVO-like calling convention. Place for return union with discriminant will be pass as one pointer to function, this storage could even be reused by next function if it return same error type. -- You received this message because you are subscribed to the Google Groups "ISO C++ Standard - Future Proposals" group. To unsubscribe from this group and stop receiving emails from it, send an email to std-proposals+unsubscribe@isocpp.org. To post to this group, send email to std-proposals@isocpp.org. To view this discussion on the web visit https://groups.google.com/a/isocpp.org/d/msgid/std-proposals/c3b7a4c0-b76a-4b23-817c-abd445c270c1%40isocpp.org. ------=_Part_8520_1785100287.1532367012993 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Monday, July 23, 2018 at 10:11:45 AM UTC+2, Nia= ll Douglas wrote:
Overall, = do we really need this 'expected' kind of type to be quite so const= rained and magic,=C2=A0to require an even address etc. etc.
In ot= her words, if the type was actually something that was specified=C2=A0as a = 'normal' C/C++ struct without any of those gymnastics and data pack= ing or=C2=A0require some carry register etc., would the code be that dramat= ically worse that we should require such magic or constraints than a regula= r type without all the magic and alignment requirements?

Not speaking for the above proposal, but in gener= al, it is currently believed that using something like the CPU carry bit ou= ght to be zero overhead on most CPUs, whereas a discriminant stored in the = layout would not be zero overhead on more CPUs.

Th= e situation of RISC-V, which has no status register, is a particular unknow= n. Our current best guess is that either we keep the discriminant in the st= ructure, or we fiddle with the return address e.g. offset it by four. There= are no good options on that architecture.

Niall= =C2=A0

On RISC-V then cost will= be same to `bool foo(void* ret)`. This will be still "zero overhead&q= uot;, simply for other architectures it will be "negative overhead&quo= t; compared to equivalent manual checks in code.

A= nother way could be use RVO-like calling convention. Place for return union= with discriminant will be pass as one pointer to function, this storage co= uld even be reused by next function if it return same error type.

--
You received this message because you are subscribed to the Google Groups &= quot;ISO C++ Standard - Future Proposals" group.
To unsubscribe from this group and stop receiving emails from it, send an e= mail to std-proposa= ls+unsubscribe@isocpp.org.
To post to this group, send email to std-proposals@isocpp.org.
To view this discussion on the web visit https://groups.google.= com/a/isocpp.org/d/msgid/std-proposals/c3b7a4c0-b76a-4b23-817c-abd445c270c1= %40isocpp.org.
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