220 30915 <4e917873-c4ea-4552-9208-b0a196399815@isocpp.org> article Path: news.gmane.org!.POSTED!not-for-mail From: "'Walt Karas' via ISO C++ Standard - Future Proposals" Newsgroups: gmane.comp.lang.c++.isocpp.proposals Subject: Re: Proposed alternative approach to specifying required memory operation ordering Date: Wed, 15 Feb 2017 14:01:47 -0800 (PST) Lines: 117 Approved: news@gmane.org Message-ID: <4e917873-c4ea-4552-9208-b0a196399815@isocpp.org> References: Reply-To: std-proposals@isocpp.org NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_2734_1002937724.1487196107380" X-Trace: blaine.gmane.org 1487196111 682 195.159.176.226 (15 Feb 2017 22:01:51 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Wed, 15 Feb 2017 22:01:51 +0000 (UTC) To: ISO C++ Standard - Future Proposals Original-X-From: std-proposals+bncBDFLZXWOVYIBBS47SPCQKGQETYNDUCQ@isocpp.org Wed Feb 15 23:01:46 2017 Return-path: Envelope-to: gclcip-std-proposals@m.gmane.org Original-Received: from mail-ua0-f197.google.com ([209.85.217.197]) by blaine.gmane.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ce7dv-00084g-6J for gclcip-std-proposals@m.gmane.org; Wed, 15 Feb 2017 23:01:43 +0100 Original-Received: by mail-ua0-f197.google.com with SMTP id j94sf122391467uad.0 for ; Wed, 15 Feb 2017 14:01:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=isocpp-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:message-id:in-reply-to:references:subject:mime-version :x-original-sender:reply-to:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-subscribe:list-unsubscribe; bh=LDhSNbGoBwJs2r32PaohLrlm9bGZSZi9nybvOKcLokE=; b=K6VG8qz49dsb+Dl38NZoepe9fKkyF5y/MupuoxQELX2LS/vNkoWsqI4/QRO9mHijXi 3l5YL/9c/pTN7HU21fdR7eMHSdi5hBXv00JCo2rEcOLLmkBEm770Zx5KUMkjvEgjG/VS Ngbu0b63Iqqc1rnG2u7fhXEFC86JG4qAHYHYQDVXXg5lY4d4SUfxsRBGDvP0fP3Yfiub D0y0KAb53KNiPQsT57EvabkL/c6hGvE+qHgUvp0EFn42qQCmAnDAJU0Qh1dAsC27x2fq zpnKN2EfpjOIgC5e2cl0softSJpv2GV+nEl9QfJiM5rX1x7YvI8R7kxJpSQtvdq3BjNU 0aSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:message-id:in-reply-to:references :subject:mime-version:x-original-sender:reply-to:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:list-subscribe:list-unsubscribe; bh=LDhSNbGoBwJs2r32PaohLrlm9bGZSZi9nybvOKcLokE=; b=VtZLhq2f4DSej8znJzSTURluP8vMcCd5t5ocI3dw7k/pgCl/EVsUunkXYrfZ7QN38t 4hEM6mZclSBF/Njyo0c161U7xlWNZCV/CCRa9gQtzt89SdoBzTlAI1TMbLeZ2yING3W8 pLABk3nCiEbFuzmDnr7RqPSWnrWLXWQIpCklXcF8qhY10jYZqJzwJINUVdAMX9FKaNjM 5/e8D/q9GhNWtWMPIPMexqnCmFJaOUpF/m8iDWl2zfFvD1MuxoEAu3EJ4YxMCYopV8pB ET0CeA/mS4mr0grS4ak1pLbrVoFZfnmHZTuHeAe9bxZagJUBxWuQqak2084jkpU98ogn vNrg== X-Gm-Message-State: AMke39mqJ6EhegRfUiYfEQQ4ugdgQKD20zEjacVzrt/Np7zIu4JFNfAtjuIjtXdgiqa9NA== X-Received: by 10.107.131.160 with SMTP id n32mr12037506ioi.47.1487196108594; Wed, 15 Feb 2017 14:01:48 -0800 (PST) X-BeenThere: std-proposals@isocpp.org Original-Received: by 10.157.3.235 with SMTP id f98ls7592298otf.16.gmail; Wed, 15 Feb 2017 14:01:47 -0800 (PST) X-Received: by 10.157.20.145 with SMTP id d17mr2894538ote.18.1487196107872; Wed, 15 Feb 2017 14:01:47 -0800 (PST) In-Reply-To: X-Original-Sender: wkaras@yahoo.com X-Original-From: Walt Karas Precedence: list Mailing-list: list std-proposals@isocpp.org; contact std-proposals+owners@isocpp.org List-ID: X-Google-Group-Id: 399137483710 List-Post: , List-Help: , List-Archive: List-Subscribe: , List-Unsubscribe: , Xref: news.gmane.org gmane.comp.lang.c++.isocpp.proposals:30915 Archived-At: ------=_Part_2734_1002937724.1487196107380 Content-Type: multipart/alternative; boundary="----=_Part_2735_1886748262.1487196107380" ------=_Part_2735_1886748262.1487196107380 Content-Type: text/plain; charset=UTF-8 On Wednesday, February 15, 2017 at 2:17:51 PM UTC-5, Walt Karas wrote: > > - In a program execution, each thread defines a nominal order of (thread > local) memory and fence operations. > - For any operations X and Y in thread T, either X before Y, or Y before X. > - A program execution defines a nominal global order of global memory > operations. > - If X and Y are atomic global operations, then either X before Y or Y > before X in the global order. > - If X is a global operation, and there exists a global store S where > neither X before S nor S before X in the global order, then the result of X > is undefined. > This rule needs the additional condition that X and S affect the same memory location. > - A program execution defines a partial function f(T, LO) -> GO where LO > is a local memory operation in thread T, and GO is a global operation. If > LO is atomic, then GO must be atomic. The result of LO is the result of > GO. If the result of GO is undefined, the result of LO is undefined. > (Even if f(T, LO) is not required to exist, it none the less _may_ exist.) > - If LO1 and LO2 are operations in thread T, and LO1 before LO2 in T, and > f(T, LO1) and f(T, LO2) both exist, then f(T, LO2) before f(T, LO1) in the > global order is not allowed. > - If: > 1. In a thread T, X and Y are memory operations, and F is a fence > operation. > 2. X before F and F before Y. > 3. F is sequentially consistent and both X and Y are atomic, or > 4. F is acquire and both X and Y are loads, or > 5. F is release and both X and Y are stores. > then F is activated for X and Y. > - In a thread T, if X and Y are memory operations (where X before Y) with > an activated fence F, then f(T, X) must exist. > - For every global operation GO, there must exist a local operation LO in > some thread T where f(T, LO) -> GO. (Assuming no intense gamma radiation.) > - A sequentially consistent (thread local) atomic memory operation implies > two sequentially consistent fences, one before and one after it (as well as > a preceding release for a store, and a succeeding acquire for a load). > -- You received this message because you are subscribed to the Google Groups "ISO C++ Standard - Future Proposals" group. To unsubscribe from this group and stop receiving emails from it, send an email to std-proposals+unsubscribe@isocpp.org. To post to this group, send email to std-proposals@isocpp.org. To view this discussion on the web visit https://groups.google.com/a/isocpp.org/d/msgid/std-proposals/4e917873-c4ea-4552-9208-b0a196399815%40isocpp.org. ------=_Part_2735_1886748262.1487196107380 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
On Wednesday, February 15, 2017 at 2:17:51 PM UTC-5, Walt = Karas wrote:
<= div>- In a program execution,=C2=A0each thread defines a nominal order of (= thread local) memory and fence operations.
- For any operations X= and Y in thread T, either X before Y, or Y before X.
- A program= execution defines a nominal global order of global memory operations.
- If X and Y are atomic global operations, then either X before Y or = Y before X in the global order.
- If X is a global operation, and= there exists a global store S where neither X before S nor S before X in t= he global order, then the result of X is undefined.

This rule needs the additional condition that X and S = affect the same memory location.
=C2=A0
- A program execution define= s a partial function f(T, LO) -> GO where LO is a local memory operation= in thread T, and GO is a global operation.=C2=A0 If LO is atomic, then GO = must be atomic. The result of LO is the result of GO.=C2=A0 If the result o= f GO is undefined, the result of LO is undefined.=C2=A0 (Even if f(T, LO) i= s not required to exist, it none the less _may_ exist.)
- If LO1 = and LO2 are operations in thread T, and LO1 before LO2 in T, and f(T, LO1) = and f(T, LO2) both exist, then f(T, LO2) before f(T, LO1) in the global ord= er is not allowed.
- If:
1.=C2=A0 In a thread T, X and = Y are memory operations, and F is a fence operation.
2.=C2=A0 X b= efore=C2=A0F and=C2=A0F before Y.
3.=C2=A0 F is sequentially cons= istent and both X and Y are atomic, or
4.=C2=A0 F is acquire and = both X and Y are loads, or
5.=C2=A0 F is release and both X and Y= are stores.
then F is activated for X and Y.
-=C2=A0In= a thread T, if X and Y are memory operations (where X before Y) with an ac= tivated fence F, then f(T, X) must exist.
- For every global oper= ation GO, there must exist a local operation LO in some thread T where f(T,= LO) -> GO.=C2=A0 (Assuming no intense gamma radiation.)
- A s= equentially consistent (thread local) atomic memory operation implies two s= equentially consistent fences, one before and one after it (as well as a pr= eceding release for a store, and a succeeding acquire for a load).

--
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To post to this group, send email to std-proposals@isocpp.org.
To view this discussion on the web visit https://groups.google.= com/a/isocpp.org/d/msgid/std-proposals/4e917873-c4ea-4552-9208-b0a196399815= %40isocpp.org.
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